1/7 october 1999 AN1156 application note connecting the mc68331 microcontroller to m29 series flash memories contents n introduction n advantages of flash n flash bus architecture n mc68331 bus architecture n timing requirements n conclusion introduction this application note describes a method of to connecting an m29f800a flash memory to an mc68331 microcontroller. the application note can be used as a reference for other flash memory devices from stmicroelectronics. the m29f800a is an 8 mbit flash memory from stmicroelec- tronics, which can be configured as a 1m byte-wide memory, or 512k word-wide memory. other flash parts that can be used in place of the m29f800a, with only minor circuit changes, in- clude the m29f400b, m29f200b and m29f100b. the tsop48 package of these memories is pin-compatible with the m29f800a, the only difference in the so44 package is the ready/busy output pin. the mc68331 is a member of motorolas 68300 family of inte- grated microprocessors. it is a general purpose 32-bit micro- controller with a wide variety of application areas including telecommunications and automotive. advantages of flash flash memories can be used to store both code and data for the mc68331 microcontroller. unlike eproms the data in flash memories can be changed by the microcontroller. this enables non-volatile user data to be stored in the flash. field upgrades of the application code can be performed without any disassembly, unlike eprom solutions. it is usual to write separate boot and application programs so that the application program can be upgraded without changing the boot program. if the upgrade fails then the processor will still boot and it will be possible to reattempt to upgrade the ap- plication. the boot code should be programmed into the flash before the flash is fitted to the circuit board, otherwise it may not be possible to boot the microprocessor. often the block containing the boot program is protected so it cannot become corrupt. flash bus architecture take a look at the bus on the m29f800a, figure 1 shows the logic diagram. the memory has separate address and data buses that can connect directly to the address and data buses on the mc68331. the control lines are chip enable (e ), output enable (g ) and write enable (w ). also, ready/busy output (r/ b ) and reset/block temporary unprotect (rp ) are present. fi- nally there is the byte pin that selects 8-bit or 16-bit mode.
AN1156 - application note 2/7 figure 1. m29f800b logic diagram the m29f800a has been designed to allow byte to change between accesses, so 8-bit accesses and 16-bit accesses can be achieved in the same design. in practice it is far simpler to always use the memory in one mode; in order to swap modes additional logic is required to decode the dq15a-1 pin, this would complicate the design, add cost and probably increase the wait-states required to access the memory. in the example here 16-bit mode has been chosen. care should be taken to make sure that all write ac- cesses will write 16-bits at a time. in order to change one byte in the memory it will be necessary to write a word. programming words and bytes takes the m29f800a the same amount of time; the internal charge pumps required for the program operation are word-wide, not byte-wide. once the choice has been made to keep byte high, the special pin, dq15aC1, can be treated like any other data input/output pin. it forms part of the data bus, dq0-dq15. note that the a0 address pin on the m29f800b specifies the address of a word, not of a byte; the address bus of the mc68331 will need to be shifted compared to the address bus of the m29f800a in order to address the flash correctly. the reset/block temporary unprotect pin (rp ) accepts three states: reset (v il ), not reset (v ih ) and block temporary unprotect (v id ). reset and not reset are the usual signals for a reset line. the mc68331 provides these signals on its reset pin. the third state, block temporary unprotect is used to temporarily unprotect blocks that have been specifically protected in the memory. many applications do not protect any blocks and therefore connect the rp pin directly to the system reset signal. figure 2 gives an example of how the connection between the mc68331s reset pin and the m29f800as rp pin can be made. the circuit makes use of a jumper to enable block temporary unpro- tect. many applications will provide the 12v from an external source, in which case the jumper can be re- placed by a connector. the advantage with the circuit, as it stands, is that a reset from the mc68331 will override block temporary unprotect and cause the flash to reset. only four additional components are required. ai02198b 19 a0-a18 w dq0-dq14 v cc m29f800at m29f800ab e v ss 15 g rp dq15aC1 byte rb
3/7 AN1156 - application note figure 2. reset/block temporary unprotect circuit before the jumper is inserted, and when reset is high, v ih , rp is connected to 5v through the 10k w resistor and the diode. the current required by rp is very low, in the order of 1 m a at 5v. the voltage drop in the resistor and the diode at these currents will keep rp very close to 5v. when the jumper is fitted the diode ceases to conduct and rp rises to 12v as the capacitor charges. the time-constant of a 10k w re- sistor and a 50pf capacitor is 500ns, satisfying the t phphh rise-time requirements of the m29f800a. dur- ing a reset, reset is low, v il , and the jfet is switched on, bringing rp close to ground. the current consumption during a reset rises due to the current through the 10k w resistor. although the use of a jumper may not be the most elegant solution, it is a practical one because it main- tains the security level offered by the block protection. there is little point in having the block temporary unprotect pin under software control. the whole point of the block protection feature is to protect against software failure. allowing the block temporary unprotect feature to be under the control of software is nearly equivalent to not protecting the blocks in the first place. mc68331 bus architecture the mc68331's bus architecture can be daunting on first appearance. there are many control lines to al- low for 8-bit accesses, 16-bit accesses, bus arbitration, memory protection (user/supervisor memory spac- es) and other complicated controls. many applications do not need to make use of these features. only a simple connection is considered here. the mc68331 uses the csboot pin to select the boot memory. this memory is mapped to 000000h at boot time, and 13 wait states are selected. there are eleven other chip selects available to control the flash if the flash is not used to boot the microcontroller. the mc68331 does not provide separate read and write control lines, instead there is only one r/w output pin. it is possible to configure the chip selects to act as chip enable, write enable and output enable for the flash memory without using any external logic. ai02937 10k w 50pf 5v 12v reset rp
AN1156 - application note 4/7 one interesting point that should be considered is the use of the m29f800as chip select. the m29f800a can be connected to the mc68331 as the boot device without any glue logic if the m29f800as chip en- able is tied to ground. the csboot pin can then be used to control output enable and cs1 can be used to control write enable. on boot csboot can be used to access the flash, cs1 can be configured in the boot code to allow write accesses to the flash. however, tying chip enable low never allows the flash to enter its standby state and the read supply current will be consumed unless automatic standby is en- tered. (automatic standby will still be entered if the address bus stops changing, e.g. if the microprocessor executes a low power stop operation). the circuit shown here makes use of an inverter to provide the correct output enable signal. figure 3. connection between the mc68331 and the m29f800a timing requirements the mc68331 has a zero wait-state external access time of about 140ns when running with a 20.97mhz clock. additional wait-states can be inserted for slower external peripherals. the timings in table 1 and figure 4 examine the read cycles timing requirements, table 2 and figure 5 examine the write cycle timing requirements; both are from the flashs perspective. a 10ns delay has been included in the mc68331 timings that affect g to account for the delay in the inverter. ai02938 19 a0-a18 w dq0-dq14 m29f800at m29f800ab e g rp dq15aC1 byte rb v cc data0-data15 addr1-addr19 mc68331 reset r/w csboot reset/block temporary unprotection circuit
5/7 AN1156 - application note table 1. read timing requirements figure 4. principal read timing waveforms from the timings it can be seen that the 55ns part is required to meet all of the timings of the 20mhz mc68331. the 70ns part is sufficient for the 16mhz mc68331. the mc68331 always leaves its chip select signal until last in any read or write cycle. the m29f800a on the other hand uses chip enable to enter the standby mode. flash access times using chip enable are always longer than the access times using output enable or write enable. the solution that ties the flash's chip enable to ground and controls accesses using output enable and write enable will allow flash memories with slower access times to meet zero wait state timing requirements. however, it will also cause the supply current to rise. m29f800a mc68331 symbol 55 70 90 f1 = 16.78 mhz dsack = 0 f1 = 20.97 mhz dsack = 0 t avav 55 70 90 150 120 t av qv 55 70 90 116 91 t elqv 55 70 90 80 57 t glqv 30 30 35 106 81 t ehqz 18 20 20 55 48 t oh 000 0 0 ai02947 tavav tavqv telqv toh a0-a17 e dq0-dq15 g tglqv tehqz data out
AN1156 - application note 6/7 table 2. write timing requirements, chip enable controlled figure 5. principal write timing waveforms, chip enable controlled conclusion the m29f800a and other stmicroelectronics flash can be connected to the mc68331 in glueless con- figurations, or with a simple inverter. the flash can be used to boot the mc68331 and provides a solution that allows field upgrades to the application software without the need to disassemble the product. m29f800a mc68331 symbol 55 70 90 f1 = 16.78 mhz dsack = 0 f1 = 20.97 mhz dsack = 0 t avav 55 70 90 150 120 t eleh 40 45 45 100 80 t dveh 25 30 45 43 33 t ehel 20 20 20 40 32 t elax 40 45 45 117 92 ai02949 tavav teleh tdveh a0-a17 e dq0-dq14 dq15aC1 w tehel data in telax
7/7 AN1156 - application note if you have any questions or suggestion concerning the matters raised in this document please send them to the following electronic mail address: ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 1999 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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